The present invention relates to methods and apparatus for providing multiple external devices with access to a single memory system.
Data processing systems with multiple asynchronous processors often include global data memory to allow data to be shared in various ways among those processors.
Storage control and management systems also may include multiple asynchronous processors and a global data memory. In this scenario, the various processors have different functions: one may be responsible for movement of data between an external computer system and the storage control system, and another may be responsible for movement of the data on and off of a disc. However, there is still the need for multiple processors to be able to read and write the data in a common memory, while it is in transit between the host and disc.
Such a common memory necessarily requires arbitration between potential users for access to the memory. One typical example might be a system built around a VME bus backplane, where all potential users have access to a common VME bus, and having arbitrated for the bus, the user has, by extension, arbitrated for use of the common memory. In such systems, a first weakness is that only one user may access the memory at a time, and other users must wait for some period of time corresponding to the number of potential users of the bus and the maximum time that one user may be on the bus.
Another weakness of this system, for the case of a storage control system, is that each element of data in transit between host and disc must transfer over the system bus twice: once to be written into the memory by the external computer, and once to be read out again by the controller for the storage control system. This effectively halves the bandwidth of the system.
It would be desirable to provide a memory in which multiple users can access various portions of the memory simultaneously. It would also be desirable to provide a memory subsystem where data did not have to travel over the same bus multiple times.